Design Verification Engineer
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Principal Recruitment Consultant at IC Resources - Semiconductor Engineering division
Are you looking for the next step in your career in UVM Verification? Would you like to learn from skilled experts in a friendly and growing environment with exciting projects? If the answer is yes, then this may be the perfect opportunity for you
I have a key requirement for an experienced/senior Verification Engineer to work for an established company based in the Grenoble area that focuses on design and verification services for a number of major clients.
As the senior verification engineer, you will be responsible for R&D projects and the development of verification environments (System Verilog / UVM /…), VIP components and giving training to other engineers.
Technical skills
- Proven experience with IP or SoC verification
- Confident knowledge of SystemVerilog and UVM methodology
- Bus communication protocols knowledge – AMBA / AXI etc.
- OOP (Object Oriented Programming) and scripting skills – Perl / shell / Python / C
- Fluent English – and preferably French
Tel – 01189073075
LinkedIn – https://www.linkedin.com/in/jordan-browne-b4a08b20b/
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