Lead Digital Design Engineer

il y a 3 semaines


Paris, Île-de-France microTECH Global Limited Temps plein
Position: Lead Digital Design Engineer
Location: Sèvres, Île-de-France
Compensation: 70,000 EUR per annum

microTECH Global Limited is at the forefront of SoC FPGA innovation, specializing in the design of proprietary chips tailored for the aerospace and defense sectors. We are expanding our software and hardware teams and are in search of a Lead Digital Design Engineer to enhance our digital design R&D division.

Key Responsibilities:
  • Serve as a senior member of the team, providing guidance and expertise on various digital design topics to junior engineers.
  • Collaborate closely with SoC HW/SW Architects and other team leaders to define SoC/IP architecture and design.
  • Engage in architecture, design, verification, implementation, testability, and validation reviews for SoC or IP projects.
  • Work alongside the Verification team to develop verification test plans.
  • Contribute to the definition of Design For Test (DFT) in partnership with the DFT team.
  • Code RTL and assist junior engineers throughout the design process.
  • Participate in the validation phase, collaborating with the validation team in your area of expertise.
  • Drive continuous improvement of digital workflows and methodologies in collaboration with other team leaders.
  • Coordinate with Backend engineers to ensure that physical implementation constraints are integrated from the architecture and specification stages.

Qualifications:
  • Master’s degree or PhD in microelectronics, electronics, or embedded systems.
  • Minimum of 10 years of industry experience with a robust understanding of digital electronics and all phases of SoC development from architecture to GDSII.
  • Familiarity with modern SoC architecture, including various CPUs, interconnects, PCIe, DDR4/5, multiple digital IPs, and peripherals; knowledge of analog IPs is advantageous.
  • Understanding of SoC power, clocking, and reset architecture.
  • Proven tapeout experience across multiple technology nodes (28nm to 3nm).
  • Proficiency in scripting languages such as Python, Perl, Bash, etc.

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