Senior DFT Engineer
il y a 3 semaines
We are seeking a highly skilled Senior DFT Engineer to join our team at RHESO.TECH, a specialized recruitment agency. As a Senior DFT Engineer, you will play a key role in the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.
Responsibilities:- Lead the definition and implementation of DFT in the chip, working closely with the physical implementation and industrialization teams.
- Develop and execute DFT flow, including HW DFT insertion, test vector generation, and validation.
- Analyze digital DFT metrics and solutions, considering DFT requirements such as test time, yield, and default rate.
- Advise digital design engineers on creating testable functional modules.
- Integrate DFT seamlessly with RTL design and physical implementation teams without SOC performance impact.
- Define optimum DFT solutions with the industrialization team and provide ATPG test vectors for production testing.
- You hold an MSc or PhD in Electrical Engineering or equivalent, with over 10 years of hands-on DFT implementation experience in complex digital and/or SOC circuits and solid knowledge in RTL design.
- You command scripting languages like TCL, Perl, Python, as well as ATPG, BIST, ECC, and Redundancy.
- You have hands-on experience with ASIC test methods and on-silicon physical and electrical defects.
- You have a strong understanding of memory tests, logic tests (boundary scan, ATPG), JTAG (IEEE1149.1, IEEE), and your plus experience with Cadence DFT design flow, large designs with advanced sub-22nm CMOS technologies.
- You demonstrate analytical and problem-solving skills, are a team player with a critical attitude and sense of initiative, and communicate fluently in oral and written English.
BAC+5, Master's Degree
RHESO.TECH, a specialized recruitment agency
Key words: DFT, Design, SOC, CMOS, ASIC, RTL, Cadence, Transceiver, Chip
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