Senior SOC DfT Design Engineer

il y a 4 semaines


Grenoble, Auvergne-Rhône-Alpes, France NXP Semiconductors Temps plein
About the Role

We are seeking a highly skilled DFT Design Engineer to join our MME team at NXP Semiconductors. As a key member of our team, you will be responsible for defining, realizing, and verifying Digital DFT functions on IPs, Subsystem or IC level based on required specifications.

Key Responsibilities
  1. Develop DFT solutions for advanced products in leading edge manufacturing technologies.
  2. Align DFT implementation with the SOC platform and IP blocks to deliver a cost-effective, high-quality implementation.
  3. Develop DFT patterns, using ATPG, which meet product test requirements for Scan Stuck-At, Transition Delay, Memory BIST, and Logic BIST.
  4. Participate in Silicon evaluation to ensure test patterns are operational immediately after silicon arrives.
  5. Stay up-to-date on best design practices and industry trends for DFT to help drive future improvements.
Requirements
  1. Master's degree in Electrical Engineering, Computer Engineering, or Electrical Computer Engineering.
  2. Good experience in DFT SoC development.
  3. JTAG Boundary Scan Design & implementation.
  4. Scan ATPG pattern generation and retargeting, ATPG GLS with timing validation.
  5. Memory BIST Algorithm development and implementation.
  6. Scan DRC and netlist quality debug.
  7. Experience with industry standard DFT tools such as Synopsys or Mentor.
  8. Fluent in English language both oral and written.

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