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Rennes, Bretagne, France INRIA Temps pleinJob DescriptionPhD Position in Reliability Enhancement of Unconventional AI AcceleratorsInria Rennes - Bretagne Atlantique Centre is seeking a highly motivated PhD student to work on the reliability enhancement of unconventional AI accelerators. The successful candidate will be part of a research team focused on developing innovative solutions for AI...
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PhD Position in Trustworthy AI Hardware Architectures
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PhD Position F/M Reliable Deep Neural Network Hardware Accelerators: Design and Development of Fault-Tolerant Architectures
Il y a 2 mois
Research Context
INRIA is seeking a highly motivated PhD student to contribute to the design and development of fault-tolerant architectures for Deep Neural Network (DNN) hardware accelerators. The goal of this project is to ensure the reliability of DNN hardware accelerators, which are critical components in various applications, including robotics, aerospace, smart healthcare, and autonomous driving.
Project Objectives
The PhD student will work on the following objectives:
- Design and develop an optimized algorithm-level fault injection framework to assess the resiliency of DNN hardware accelerators to hardware faults.
- Design selective fault-tolerance approaches for DNN hardware accelerators using the analysis provided by the fault injection method.
- Measure the reliability improvements obtained with the above-described methodology and perform a design space exploration to obtain different DNN hardware accelerator implementations providing different trade-offs between fault tolerance and energy efficiency.
Methodology
The PhD student will use a divide and conquer approach to reduce the fault injection complexity. Local fault injections will be performed at the layer/kernel levels to avoid running the full inference. Solid and efficient approaches will be designed to link the local sensitivity to the global accuracy.
Expected Outcomes
The expected outcomes of this project include:
- An optimized accelerated fault injector framework enabling large-scale fault simulations.
- Error correction mechanisms, such as selective low-precision triplication using checkers/voters, most-significant bits reinforcement, standby sparing, and correcting codes.
- A design space exploration to find the best solutions in terms of trade-off between the fault tolerance level provided by detection/correction mechanisms and the hardware overhead entailed deploying these solutions.
Requirements
The candidate must have a Master's degree in Computer Science, Computer Engineering, or Electrical Engineering. Required technical skills include good knowledge of computer architectures and embedded systems, HW design, basic programming knowledge, basics of Machine Learning, and experience with High Level Synthesis (HLS) and fault-tolerant architectures. Proficiency in written English and fluency in spoken English or French are required. The candidate will work in a research team and must be able to present the progress of their work in a clear and detailed manner.
Benefits
The PhD student will benefit from a monthly gross salary amounting to 2000 euros for the first and second years and 2100 euros for the third year. Subsidized meals, partial reimbursement of public transport costs, possibility of teleworking, and flexible organization of working hours are also offered.