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PhD Position F/M Reliable Deep Neural Network Hardware Accelerators: Design and Development of Optimized Algorithm-Level Fault Injection Framework
il y a 1 mois
INRIA is seeking a highly motivated PhD student to work on the design and development of an optimized algorithm-level fault injection framework for assessing the resiliency of Deep Neural Network (DNN) hardware accelerators to hardware faults. The goal of this project is to enable the application of low-cost selective fault-tolerance strategies and to design selective fault-tolerance approaches for DNN HW accelerators.
Key Responsibilities:
- Design and develop a methodology to perform large-scale fault analysis on state-of-the-art DNN hardware architectures.
- Develop a fault injection framework to assess the resiliency of DNN HW accelerators to hardware faults.
- Design selective fault-tolerance approaches for DNN HW accelerators using the analysis provided by the fault injection method.
- Measure the reliability improvements obtained with the above-described methodology and perform a design space exploration to obtain different DNN HW accelerator implementations providing different trade-offs between fault tolerance and energy efficiency.
Requirements:
- Master's degree in Computer Science, Computer Engineering, or Electrical Engineering.
- Good knowledge of computer architectures and embedded systems.
- HW design: VHDL/Verilog basics, HW synthesis flow.
- Basic programming knowledge (C/C++, python).
- Basics of Machine Learning (pytorch/tensorflow).
- Experience with High Level Synthesis (HLS) is a plus.
- Experience in fault tolerant architectures is a plus.
Working Conditions:
- Subsidized meals.
- Partial reimbursement of public transport costs.
- Possibility of teleworking (90 days per year) and flexible organization of working hours.
- Partial payment of insurance costs.
Salary: monthly gross salary amounting to 2000 euros for the first and second years and 2100 euros for the third year.