Rtl Design Engineer

**REF: RTLE**:
Montbonnot-Saint-Martin or Sophia Antipolis / Permanent

**To support our growth, we are hiring an RTL Engineer**:
REF: RTLE

**ABOUT KALRAY**:
Kalray is a European **leader in hardware acceleration**, with full-stack acceleration expertise: from silicon to complete system.

Our **MPPA® (Massively Parallel Processor Array)** architecture is the foundation of Kalray’s processor (30+ patent families, 15+ years of development) and acceleration cards that combine processing power, flexibility, and energy efficiency.

Our mission is to deliver open **data-efficient hardware accelerators** to power next generation of data-intensive, AI-driven systems and infrastructures. We offer off-the-shelf processors, acceleration cards, and specialized processor development.

With over **130 employees** and presence in France and Romania, Kalray is backed by top-tier investors and publicly listed on **Euronext Growth.**You’ll be part of a pioneering team that is shaping the future of computing with cutting-edge **processor architecture, software-defined solutions,**and **next-generation acceleration platforms.**

We offer a **fast-paced, inclusive, and collaborative environment** where ambitious experienced professionals and young talents can thrive—while enjoying the positive and inspiring lanscape of the Alps or the Côte d’Azur.

**WHAT YOU 'LL BE DOING**:
As an **RTL Designer,**you will be part of the **HW Design team (15 people)**and contribute to th**e full development lifecycle**of our next-generation high-performance processors on advanced technology nodes.

You’ll work on cutting-edge challenges, from **microarchitecture design to power-aware RTL implementation**, encompass the IP and subsystem specifications, the micro architecture, the design, and the synthesis of various blocks inside the chip. You will collaborate closely with physical design and verification teams.

**Responsibilities**:

- Take part in ASIC architecture in collaboration with the system architecture team
- Specify, design, implement, and debug RTL blocks for various high-end SoC components
- Optimize area and power to meet aggressive **PPA (Performance, Power, Area)**targets
- Stay up-to-date with state-of-the-art digital architectures and industry trends
- Collaborate with verification and physical design teams throughout the project lifecycle

**WHAT WE ARE LOOKING FOR**:
**Skills**:

- RTL design (VHDL or Verilog)
- Familiar with Clock and reset scheme, Synthesis and SDC constraints, formal proof, CDC structures
- Fluent in technical English
- Good communication / reporting skills
- Capable of managing a small team (contractors,partners, junior people)

**Profile**:

- Graduate Engineer or equivalent
- 5 years+ in ASIC or FPGA digital RTL for commercial products.
- Experience in SOC interconnects dimensioning, high speed interface design/integration (PCI, Ethernet or DDR), processors design/integration would be a plus.
- Curious, autonomous, Rigorous
- Strong teamwork skills

**CONTRACT INFORMATION**:

- Type of contract: Permanent contract
- Starting date: As soon as possible
- Location: Montbonnot St Martin or Sophia Anrtipolis

**WHAT WE CAN OFFER YOU**:

- Competitive salary & performance-based RSU (free shares)
- Hybrid work model
- Additional paid leave (RTT)
- Meal vouchers (Edenred)
- Premium health coverage (Malakoff Humanis)
- Sustainable mobility incentives
- Generous paternity leave
- Monthly team activities (laser game, hiking, sailing, karaoke) and large-scale company events

**RECRUITMENT PROCESS**:

- First interview with the manager
- Second interview with the team
- Final interview with HRD or CEO

**Equal Opportunity Statement**: