Hardware Program Lead

il y a 3 jours

Avenue du Maine Paris France Aico Technology Temps plein

You will join AICO as a Hardware Lead, responsible for leading the design and industrialization of our ASIC based on an innovative compute architecture (NPU-like) dedicated to Spiking Neural Network (SNN) inference for embedded systems.

You will lead the Digital Design team (RTL/FPGA/ASIC engineers) and own the roadmap, specification, quality, and delivery of the chip. You will work closely with external partners (physical design/back-end, foundries, packaging, test, IP vendors, etc.) to drive the project end-to-end through tape-out and early bring-up.

In a small team, this is also a hands-on role: you will contribute to architectural decisions, RTL and verification strategy, and key PPA (Power/Performance/Area) trade-offs, while setting up robust development processes and ensuring execution.

Key responsibilities

  • ASIC program leadership: define specs, plan and milestones (tape-out, bring-up), manage risks, track quality/cost/schedule.

  • Technical leadership: review/validate architecture and micro-architecture, drive PPA trade-offs, define performance/power/area and interface requirements.

  • Team leadership: manage and mentor RTL/FPGA engineers, run design reviews, prioritize work, raise engineering standards.

  • Partner management: coordinate with physical design (synthesis/P&R/STA), DFT, verification, foundry, packaging, test, validation partners.

  • Methodology & flow: establish/maintain ASIC development flow (lint, CDC, simulation, regressions, sign-off criteria), configuration management and release process.

  • Prototyping & validation: leverage FPGA prototyping/demos to de-risk the ASIC and prepare bring-up.

  • Hands-on RTL contribution: occasionally contribute directly to RTL development (implementing critical blocks, prototyping, code reviews/merges) and supporting the team on complex or time-critical topics.

  • FPGA demonstrator contribution: occasionally contribute directly to the building of FPGA demonstrators.

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