Internship RISC-V matrix/vector ISA extension Benchmark-Grenoble-H/F

Position description Category Micro and nano technologies Contract Internship Job title Internship RISC-V matrix/vector ISA extension Benchmark-Grenoble-H/F Subject investigate open source RISC-V matrix/vector ISA extension performance impact based on high level simulation tools. The subject encompasses ISA extension design identification and installation with adequate software chain, workload slection and performance evaluation. Contract duration (months) 6 mois

Job Description
As an intern at the CEA, you will have the opportunity to work within a world-renowned research environment. Our teams consist of passionate and dedicated experts, providing an ideal setting for learning and collaboration. You will have access to state-of-the-art equipment and top-tier research resources to carry out your assignments. The work conducted may potentially lead to a scientific publication. Internship Description This internship will take place within a group specializing in the design of energy-efficient digital integrated circuits. An embedded computing platform based on RISC-V CPUs is available, targeting either bare-metal computing (RV32) or the booting of an embedded operating system (CVA6). The intern will be responsible for identifying existing open-source matrix/vector ISA extension, installing the best forks (namely 2), including software chain (gcc, linker) and setting up a benchmark test suite adapted to the context of embedded low-energy computation, like EEMBC, data movement compression, error correction, signal processing, convolutions, non-linear activation functions, using vector and matrix computations [1-2], Preliminary work on the ARA platform done in the lab, will allow the intern to become familiar with the existing setup [3-4]. The primary objective of this internship is to benchmark and analyze the performance of RISC-V vector and matrix ISA extensions. This will involve profiling the performance and resource utilization of different RISC-V implementations with these extensions enabled, using RTL simulators and/or architectural emulators (e.g., QEMU). If time allows, the chosen architectures will be mapped on ASIC technology to include performance evaluation with the impact of back-end non-idealities. The secondary objective is to investigate potential improvement of the lab’s offering in the compute domain. Conditions This internship is intended for master (or engineering school) students in their last year. It is possible to base the master’s thesis on the subjects treated during the internship. The student will have a 6-month remunerated stage contract, plus benefits for accommodation in Grenoble and public transportation. References [1] XUANTIE-RV [2] quadrilatero [3] ara [4] lab's RISCV summit 2026 poster Useful links https://www.cea.fr/english | https://list.cea.fr/en/ | https://maps.app.goo.gl/rD6qoGjxWvJuvYHy6 # CEA-List Methods / Means gcc compilation and linker, RTL/systemC simulation, synopsys design exploration if time allows Applicant Profile This offer is dedicated to engineering degree / master students looking for an ambitious research-oriented internship. Candidates should have a background in electronic or computer engineering, with solid knowledge of computer architectures and digital design. It is desirable to have familiarity with RISC-V microprocessors or architectural simulators. Knowledge on SystemC, Git data-management, UNIX scripting is a plus. Position location Site Grenoble Job location France, Auvergne-Rhône-Alpes, Isère (38) Location GRENOBLE Candidate criteria Languages
• French (Fluent)
• English (Intermediate) Prepared diploma Bac+5
- Diplôme École d'ingénieurs Recommended training Ecole d'électronique PhD opportunity Non Requester Position start date 01/03/2027