PhD thesis: Graph Neural Networks for Predicting Power Consumption in Digital Electronic Architectures
Il y a 2 mois
Description de l'offre
Power consumption analysis is an important step in the development of a digital architecture. This power analysis is necessary early on in the RTL (Register Transfer Level) coding stage when the most advantageous modifications can be made. As designs become larger, power analysis relies on longer simulation traces and becomes nearly impossible because the process generates huge simulation files, resulting in long power analysis execution times. To address this issue, power models can be used to accelerate this analysis stage. There is a wide range of research on power modeling at the RTL level, mainly based on analytical or learning approaches. Analytical power modeling attempts to correlate application profiles such as memory behavior, branch behavior, etc., with microarchitecture parameters to create a power model. Meanwhile, learning-based power modeling generates a model based on the simulation trace of the design and a reference power close to actual consumption. Learning-based power modeling is gaining popularity as it is easier to implement than the analytical approach and does not require extensive design knowledge. These ML-based methods have shown impressive improvements over analytical methods. However, classical ML methods (linear regression, neural networks, etc.) are more suitable for generating a model for a specific architecture, making them difficult to use for generating a generalizable model. Thus, in the past two years, some studies have begun using graph neural networks (GNNs) to address model generalization in the field of electronic design automation (EDA). The advantage of a GNN over classical ML approaches is its ability to learn directly from graphs, making it more suitable for EDA problems.
The objective of this thesis is to design a generalizable power consumption model for a digital electronic architecture based on GNN. The developed generalizable model should be capable of estimating, in addition to average consumption, the cycle-by-cycle consumption of any digital electronic architecture. Very few works exist in the state of the art on the use of GNNs for consumption estimation, and the models designed in these works are only capable of estimating the average consumption of an architecture. Moreover, several important research questions are not addressed in these works, such as:
Thus, during this thesis, these questions will be studied to understand their impact during model generation.
The data generated by the GNN, or Graph Embeddings, are then fed into another model. This model can be a conventional neural network, a transformer, or a Large Language Model (LLM). During this thesis, identifying the optimal model to facilitate generalization will also be an area of exploration.
Profil du candidat
Master's degree in computer science/electronics. Good experience/knowledge in machine learning. Experience/knowledge in digital electronics design is also a plus. Excellent Python programming skills. Proficiency in VHDL and/or Verilog programming would be a plus. Strong analytical and experimental skills will be highly appreciated.-
SACLAY, France CEA Temps pleinPower consumption analysis is an important step in the development of a digital architecture. This power analysis is necessary early on in the RTL (Register Transfer Level) coding stage when the most advantageous modifications can BE made. As designs become larger, power analysis relies on longer simulation traces and becomes nearly impossible because the...
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SACLAY, 91400, Palaiseau, France CEA Temps pleinPower consumption analysis is an important step in the development of a digital architecture. This power analysis is necessary early on in the RTL (Register Transfer Level) coding stage when the most advantageous modifications can BE made. As designs become larger, power analysis relies on longer simulation traces and becomes nearly impossible because the...
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Saclay, France Cea Temps pleinPower consumption analysis is an important step in the development of a digital architecture. This power analysis is necessary early on in the RTL (Register Transfer Level) coding stage when the most advantageous modifications can be made. As designs become larger, power analysis relies on longer simulation traces and becomes nearly impossible because the...
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