Emplois actuels liés à PhD Position in AI-Assisted Generation of High-Level Models and Simulators for Hardware Design - Palaiseau, Île-de-France - Cea
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Palaiseau, Île-de-France CEA Temps pleinJob Title:PhD Position in AI-Assisted Generation of High-Level Models and Simulators for Hardware DesignJob Description:The CEA is seeking a highly motivated PhD student to work on a research project focused on the development of AI-assisted generation of high-level models and simulators for hardware design. The successful candidate will be part of a team...
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Palaiseau, Île-de-France CEA Temps pleinJob SummaryWe are seeking a highly motivated PhD researcher to join our team at CEA, working on the development of AI-assisted generation of high-level models and simulators for hardware design.Key ResponsibilitiesDesign and implement a methodology for automatic generation of Instruction Set Simulators (ISSs) from Register Transfer Level (RTL) models using...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: PhD Position in AI-Assisted Generation of High-Level Models and SimulatorsCategory: Electronics components and equipmentsContract: Fixed-term contractSocio-professional category: Non CadreContract duration (months): 36Job description:The design and validation of digital circuits rely heavily on simulation tools. These tools employ different levels...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsJob Description:We are seeking a highly skilled Research Engineer to join our team at CEA, a leading research organization in the field of Electronic Design Automation (EDA). As a Research Engineer, you will play a key role in developing cutting-edge...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team at CEA to develop cutting-edge technology in the field of Electronic Design Automation (EDA).Job SummaryThe successful candidate will be responsible for developing a simulation environment...
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Palaiseau, Île-de-France CEA Temps pleinResearch Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team and contribute to the development of cutting-edge technology in Electronic Design Automation (EDA). The successful candidate will be responsible for developing a simulation environment for chiplet-based...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team at CEA to develop cutting-edge technology in the field of Electronic Design Automation (EDA).Job SummaryThe successful candidate will be responsible for developing a simulation environment...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team at CEA to develop cutting-edge technology in the field of Electronic Design Automation (EDA).Job SummaryThe successful candidate will be responsible for developing a simulation environment...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsJob Description:We are seeking a highly skilled Research Engineer to develop cutting-edge technology in the field of Electronic Design Automation (EDA). The successful candidate will be responsible for developing a simulation environment for chiplet-based...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team at CEA to develop cutting-edge technology in the field of Electronic Design Automation (EDA).Job Description:The successful candidate will be responsible for developing a simulation...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team at CEA to develop cutting-edge technology in the field of Electronic Design Automation (EDA).Job Description:The successful candidate will be responsible for developing a simulation...
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Palaiseau, Île-de-France CEA Temps pleinResearch Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsCEA is seeking a highly skilled Research Engineer to join our team and contribute to the development of cutting-edge technology in the field of Electronic Design Automation (EDA).Key Responsibilities:Develop and implement AI-based model generation methodologies for...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team at CEA to develop cutting-edge technology in the field of Electronic Design Automation (EDA).Job SummaryThe successful candidate will be responsible for developing a simulation environment...
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Palaiseau, Île-de-France CEA Temps pleinJob Title: Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC DesignsWe are seeking a highly skilled Research Engineer to join our team at the French Alternative Energies and Atomic Energy Commission (CEA) to develop cutting-edge technology in the field of Electronic Design Automation (EDA).About the RoleThe successful...
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Palaiseau, Île-de-France CEA Temps pleinJob DescriptionWe are seeking a highly skilled Research Engineer to join our team at the French Alternative Energies and Atomic Energy Commission (CEA). The successful candidate will be responsible for developing cutting-edge technology in the field of Electronic Design Automation (EDA) with a focus on AI-assisted methods for model generation and simulation...
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Palaiseau, Île-de-France CEA Temps pleinJob SummaryWe are seeking a highly skilled Research Engineer to join our team at CEA, focusing on developing cutting-edge technology in Electronic Design Automation (EDA). The successful candidate will be responsible for developing a simulation environment for chiplet-based SoC architecture, leveraging AI-driven methodologies to enhance existing EDA flow.Key...
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Palaiseau, Île-de-France CEA Temps pleinJob SummaryWe are seeking a highly skilled Research Engineer to develop cutting-edge technology in Electronic Design Automation (EDA). The successful candidate will be responsible for developing a simulation environment for chiplet-based SoC architecture, using AI-driven methodologies to improve existing EDA flow.Key ResponsibilitiesDevelop and implement...
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Palaiseau, Île-de-France CEA Temps pleinJob DescriptionWe are seeking a highly skilled Research Engineer to join our team at CEA List, a research laboratory specializing in intelligent digital systems. The successful candidate will be responsible for developing cutting-edge technology in the field of Electronic Design Automation (EDA).The generated models will cover functional behavior for...
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PhD Position in Scalable Naming Service Design
il y a 4 semaines
Palaiseau, Île-de-France Inria Temps pleinAbout the Centre or DepartmentThe Inria Saclay-Île-de-France Research Centre is a leading institution in the field of computer science and mathematics. Established in 2008, it has developed a strong partnership with Paris-Saclay University and the Institut Polytechnique de Paris. The centre has 40 project teams, 32 of which operate jointly with Paris-Saclay...
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Palaiseau, Île-de-France Inria Temps pleinAbout the Centre or DepartmentInria Saclay-Île-de-France Research Centre was established in 2008 and has developed as part of the Saclay site in partnership with Paris-Saclay University and the Institut Polytechnique de Paris.The centre has 40 project teams, 32 of which operate jointly with Paris-Saclay University and the Institut Polytechnique de Paris....
PhD Position in AI-Assisted Generation of High-Level Models and Simulators for Hardware Design
Il y a 3 mois
Simulation tools are essential for the design and validation of digital circuits. They use different levels of abstraction to facilitate hardware/software co-design and co-validation. Architecture simulators, called Instruction Set Simulators (ISSs) , provide high-level abstraction for fast functional verification and early design space exploration, while Register Transfer Level (RTL) simulators provide detailed circuit-level implementation for accurate analysis but with longer simulation times.
Faced with accelerated development schedules together with tool and resource constraints, hardware designers often start with RTL development and defer the construction of an ISS. However, as the design process progresses, the need to create ISSs becomes apparent, particularly for tasks such as software validation and design space exploration of next-generation hardware.
Creating ISSs manually presents significant challenges, as it is both time-consuming and error-prone. Further complexity is introduced by the need to ensure equivalence between ISS and RTL. There is therefore an urgent need for innovative methods to automate the generation of an ISS when the RTL is available.
The generation process of an ISS consists mainly of extracting architectural states and deriving instruction execution functions [1, 2]. An ISS is then constructed by seamlessly integrating the architectural states and the instruction execution functions, ensuring an accurate representation of the hardware's functional behaviour.
The goal of the thesis is to design a methodology implemented in a tool that takes low-level RTL models as input and automatically generates an ISS by exploiting recent advances in machine learning (ML) such as Graph Neural Networks [3], and compilation flows such as MLIR [4], in the field of electronic design automation (EDA) . The expected result is a complete flow for the automatic generation of ISS from RTL, ensuring by construction the semantic consistency between the two levels.
The results of this thesis will be the subject of presentations at international conferences and in scientific journals.
References
[1] Zeng, Yu, Aarti Gupta, and Sharad Malik. "Generating architecture-level abstractions from RTL designs for processors and accelerators part I: Determining architectural state variables." ICCAD, 2021.
[2] Zeng, Yu, Aarti Gupta, and Sharad Malik. "Automatic generation of architecture-level models from RTL designs for processors and accelerators." DATE, 2022.
[3] Chowdhury, Subhajit Dutta, Kaixin Yang, and Pierluigi Nuzzo. "ReIGNN: State register identification using graph neural networks for circuit reverse engineering." ICCAD, 2021.
[4] Lattner, Chris, et al. "MLIR: Scaling compiler infrastructure for domain specific computation." CGO, 2021.
Profil recherché
- Master's degree in Computer Science/Electronics.
- Good experience/knowledge in Machine Learning.
- Experience/knowledge in digital electronics design.
- Excellent programming skills in Python and C++. Proficiency in VHDL and/or Verilog programming will be a plus.
- Good analytical and experimental skills will be highly valued.
In accordance with the commitments made by the CEA in favor of the integration of people with disabilities, this job is open to everyone.
Présentation de Cea
Le CEA est un acteur majeur de la recherche, au service des citoyens, de l'économie et de l'Etat.
Il apporte des solutions concrètes à leurs besoins dans quatre domaines principaux : transition énergétique, transition numérique, technologies pour la médecine du futur, défense et sécurité sur un socle de recherche fondamentale. Le CEA s'engage depuis plus de 75 ans au service de la souveraineté scientifique, technologique et industrielle de la France et de l'Europe pour un présent et un avenir mieux maîtrisés et plus sûrs.
Implanté au cœur des territoires équipés de très grandes infrastructures de recherche, le CEA dispose d'un large éventail de partenaires académiques et industriels en France, en Europe et à l'international.
Les collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales :
• La conscience des responsabilités
• La coopération
• La curiosité
