User Terminal RF Systems Architect UT Modem Antenna

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We are looking for an RF systems architect to own the radio chain of Eutelsat's next generation LEO, multi-orbit and IRIS² user terminals, from the data converters of the modem SoC to the radiating aperture of an electronically steered array in Ku and Ka band. The centre of gravity of the role is the modem to antenna interface: the document that defines it, the budgets that sit behind it, and the discipline of keeping both consistent as two subsystems are developed in parallel by different organisations.

Much of the hardware is designed by external partners and integrators. Your role is to understand their designs well enough to own the outcome: to hold the RF budgets, to allocate impairments between the radio and the physical layer with our modem architect, to review and challenge what is proposed, and to accept it on measured evidence. You will work daily with the modem architecture and verification engineers, and you will be the RF counterpart in every technical review with our partners.

This is a founding role in a capability under construction. The budgets, the interface documents, the measurement plans and the review practices are still to be created, in a programme that moves at constellation pace. Regulatory conformance and type approval are handled elsewhere in the organisation, so the focus here is engineering performance rather than certification.

What you'll do

• Own the modem to antenna interface control document and keep it alive through the programme: digital and analogue signal interfaces, JESD204D/E lane rates, subclass and deterministic latency, analogue IQ alternatives, sampling and clocking plan, reference and 1PPS distribution, control and telemetry plane, beam pointing and beam switching commands with their latency, calibration data flow, gain and AGC partitioning between antenna and modem, power sequencing, and the thermal and mechanical boundary conditions;
• Own the end to end RF budgets and their traceability to service performance: G/T and EIRP at terminal level, noise figure and gain cascade, linearity and intermodulation, power amplifier back-off and efficiency, spurious and harmonics, image rejection and IQ imbalance, frequency and LO plan with spur analysis, and filtering and selectivity against adjacent systems;
• Own the phase noise budget across reference oscillator, PLL and synthesisers, converter clocking and SYSREF distribution, and translate it with the modem architect into its effect on carrier phase tracking, EVM and demodulation margin;
• Allocate the impairment budget between the radio chain and the phys