Senior Digital Verification Engineer — Lead UVM

Il y a 4 jours

Rennes, Bretagne, France VLSI Temps plein 90 000 € - 120 000 € Contrat

Cadence Design Systems, Inc. is seeking a Senior Digital Verification Engineer to lead robust UVM verification environments for high-performance ASIC designs.

You will drive verification strategy, automate large-scale regression flows, and mentor a verification team across cross-functional groups. Responsibilities include scalable test-bench architectures, reusable verification components, and achieving full functional and code coverage before RTL freeze.