Senior Digital Verification Engineer — Lead UVM
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Cadence Design Systems, Inc.
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is seeking a Senior Digital Verification Engineer to lead robust UVM verification environments for high-performance ASIC designs.
You will drive verification strategy, automate large-scale regression flows, and mentor a verification team across cross-functional groups. xuezdbg
Responsibilities include scalable test-bench architectures, reusable verification components, and achieving full functional and code coverage before RTL freeze.
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