Senior RTL Verification Engineer
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Arteris recrute un Design Verification Engineer pour rejoindre les flux d’assemblage SoC et le Register Bank Compiler. Vous contribuerez à garantir la qualité et la robustesse des outils et livrables au sein d’un contexte NoC/EDA avancé.
Le candidat idéal possède 7+ années d’expérience en vérification RTL, maîtrise l’UVM et les langages RTL, ainsi qu’une solide compétence en Python et en anglais technique.
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