Senior Debug, Trace

Il y a 3 jours

La Ciotat, Provence-Alpes-Côte d'Azur, France SiFive, Inc. Temps plein 110 000 € - 150 000 € Contrat

SiFive is seeking a hardware design technical lead focused on debug, trace and profiling IP to accelerate the adoption of RISC-V across SOC designs. You will help shape a highly configurable line of processor cores and lead the hardware design team in RTL development using Chisel/FIRRTL.

The role involves collaboration with architecture, performance, software and hardware teams, and engagement with customers and partners to evolve debugging solutions.