Senior Digital Verification Lead

Il y a 23 heures

CessonSévigné, Bretagne, France SECURE IC - France Temps plein

Cadence Design Systems, Inc.

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in France (Rennes/Paris) seeks a Senior Digital Verification Engineer to lead the development and execution of robust UVM verification environments for high‑performance ASIC designs.

You will drive verification strategy, automate large‑scale regression, and mentor a team across cross‑functional groups.

The role requires 7–10 years in digital verification, xuezdbg strong SystemVerilog/UVM skills, Cadence Xcelium expertise, and hands‑on experience with constrained‑random and