Verification Engineer

Senior Staff ASIC Verification EngineerOverview/Job SummeryWe are looking for a highly experienced Senior Staff ASIC Verification Engineer to lead the verification of complex digital designs.

Bien que l'expérience professionnelle et les qualifications soient essentielles pour ce poste, assurez-vous de vérifier que vous possédez les compétences non techniques souhaitables avant de postuler, si nécessaire.

The ideal candidate will have deep expertise in advanced verification methodologies, strong leadership skills, and a proven track record of successfully verifying sophisticated SoCs/ASICs from concept to silicon.

Job Description
Technical LeadershipLead end-to-end verification of complex digital IP blocks and subsystemsDefine and implement comprehensive verification strategies and test plansDevelop advanced UVM testbench architectures and reusable verification componentsDrive coverage closure and sign-off quality metricsPerform block-level and system-level verificationMethodology & InfrastructureDevelop and enhance verification methodologies and flowsCreate and maintain advanced verification infrastructure using Python/Perl/TCL scriptingBuild behavioral models and reference models for complex protocolsImplement coverage-driven and assertion-based verification strategiesOptimize simulation performance and regression efficiencyCollaboration & MentorshipWork closely with design, architecture, system, and physical implementation teamsProvide technical mentorship to junior and mid-level verification engineersConduct design and testplan reviewsLead debug efforts for complex functional and timing issuesDrive best practices and process improvements across the verification teamProject LeadershipOwn verification schedules and deliverables for assigned blocksIdentify project risks and develop mitigation strategiesPresent verification status and quality metrics to managementParticipate in post-silicon validation and debugQualificationsExperience10+ years of hands-on ASIC/FPGA verification experience5+ years of experience with UVM methodologyProven track record of multiple successful tape-outsExperience leading verification projects from specification to siliconTechnical SkillsVerification Methodologies:Expert-level proficiency in SystemVerilog and UVMDeep understanding of constrained random verificationFunctional coverage and code coverage analysisAssertion-based verification (SVA)Experience with formal verification tools (bonus)Tools & Simulators:Required: Cadence simulation tools (Xcelium/IES/SimVision)Highly Preferred: Synopsys VCS and DVEExperience with debug tools and waveform viewersFamiliarity with coverage tools (IMC, URG, or equivalent)Scripting & Programming:Strong proficiency in Python and/or PerlExperience with TCL scriptingShell scripting (bash/csh)Makefile developmentFamiliarity with version control (Git, SOS)Modeling:C/C++ or SystemC for reference model developmentBus functional models (BFM) developmentProtocol monitors and checkersPerformance modeling experience (plus)Technical Knowledge:Strong understanding of RTL design principlesExperience with industry-standard protocols (e.g., AMBA AHB/APB,I2C/SPI/I3C,..

etc.)Knowledge of low-power verification techniques (UPF)Knowledge of Gate Level Simulation verificationEducationBS in Electrical Engineering, Computer Engineering, or Computer Science requiredMS or PhD preferredPreferred QualificationsExperience with Synopsys VCS simulator and associated toolsFormal verification experience (JasperGold, VC Formal)Post-silicon validation and bring-up experienceExperience with RISC-V, or other processor architecturesMixed-signal verification experienceKnowledge of machine learning/AI accelerator verificationKey CompetenciesTechnical Excellence:Deep analytical and problem-solving skillsAbility to debug complex, multi-million gate designsStrong understanding of verification quality metricsLeadership & Communication:Excellent written and verbal communication skillsAbility to mentor and develop engineering talentCross-functional collaboration and influenceTechnical presentation skillsPersonal Attributes:Self-motivated with strong ownership mentalityDetail-oriented with quality focusAdaptable to changing prioritiesPassion for innovation and continuous learningApplication ProcessInterested candidates should submit:1.     Current resume/CV2.     Cover letter highlighting relevant experience3.     Links to any publications or GitHub projects (optional)InvenSense, a TDK group company, is a world-leading provider of MEMS and magnetic sensor solutions found in mobile, wearable, smart home, AR/VR, and other consumer and IoT applications.

We are innovators with a 20+ year history of patented sensor technologies. xuezdbg

As experts in our field, we lead industry breakthroughs in consumer, industrial and automotive technology and reliably deliver high-quality solutions to our partners across global markets.

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