Internship - Technology & Cost Analyst - Computing
Il y a 3 jours
SucésurErdre, Pays de la Loire, France
Yole Group
Temps plein
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Our
company proposes a 6 months internship for Technology
& Cost Analyst trainee to
help us to further develop & support our Computing Department.
The
core objective of this internship is
to oversee the technology and industry insights from manufacturing trends and
design of different computing &
memory semiconductor devices
to estimate production cost and understand the
related manufacturing processes.
You will
particularly work on gate-all-around
(GAA/GAAFET) transistor technologies, on memories and logic chips.
The position
is only opened to Master's students in engineering and based near Nantes
(44).
As
a Technology & Cost Analyst Trainee, your main tasks will be to:
• Interact with the laboratory analysts to follow the physical analysis of devices (chemical and mechanical opening, optical and SEM microscope inspection, cross-sections…)
• Learn how to use internal costing tools to simulate the costs
• Research the manufacturing process flow of 2 nm logic chips based on gate-all-around (GAA) transistors
• Participate in developing and verifying process flow models through teardown results, survey and publication research
• Compare cost simulation approaches and feed the results into our digital platform Requirements PROFILE
• A Master's student in Microelectronics, Nanotechnology, Materials engineering or a related subject
• Deep knowledge of semiconductors and interest for advanced technologies
• Excellent English speaking/writing is mandatory (minimum CECR
- B2 / TOEIC 785)
• Good knowledge of Excel, PowerPoint and AI tools
• Autonomous, proactive, rigorous with good analytical and synthetical skills
• Interact with the laboratory analysts to follow the physical analysis of devices (chemical and mechanical opening, optical and SEM microscope inspection, cross-sections…)
• Learn how to use internal costing tools to simulate the costs
• Research the manufacturing process flow of 2 nm logic chips based on gate-all-around (GAA) transistors
• Participate in developing and verifying process flow models through teardown results, survey and publication research
• Compare cost simulation approaches and feed the results into our digital platform Requirements PROFILE
• A Master's student in Microelectronics, Nanotechnology, Materials engineering or a related subject
• Deep knowledge of semiconductors and interest for advanced technologies
• Excellent English speaking/writing is mandatory (minimum CECR
- B2 / TOEIC 785)
• Good knowledge of Excel, PowerPoint and AI tools
• Autonomous, proactive, rigorous with good analytical and synthetical skills