Internship Hybrid DRAM: Next-Gen ferroelectric memory for energy-constrained systems-Grenoble-H/F

Il y a 18 heures

Grenoble, Auvergne-Rhône-Alpes, France CEA Temps plein

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As an intern at the CEA, you will have the opportunity to work within a world-renowned research environment. Our teams consist of passionate and dedicated experts, providing an ideal setting for learning and collaboration. You will have access to state-of-the-art equipment and top-tier research resources to carry out your assignments. The work conducted may potentially lead to a scientific publication. Context : Hafnium–zirconium oxide (HZO) ferroelectric stacks enable the development of highly scalable memories compatible with CMOS fabrication processes. These technologies offer the potential for integration densities comparable to those of DRAM, while supporting both volatile and non-volatile operating modes. What do we expect from you? The objective of this internship is to assess the potential of these hybrid memories for energy-constrained systems through the design and evaluation of critical circuit blocks. This work will contribute to establishing a design basis for future hybrid memory architectures. During the internship, the student will design circuits of key building blocks of a memory subarray, such as sense amplifiers and replica timing paths, using industry-standard circuit design and simulation tools. The resulting circuits will be evaluated in terms of timing performance, power and energy consumption, and operating stability. # CEA-List Moyens / Méthodes / Logiciels Outils de conception et de simulation électrique (Spice) Profil du candidat Desired Skills And Experience This internship is intended for students in the final year of a Master’s degree or engineering programme, preferably with a background in electronics, microelectronics, or embedded systems. Solid circuit design skills, particularly in schematic capture and SPICE simulation and language, are desirable, together with a good understanding of memory hierarchies and low-power design principles. The internship can form the basis of a PhD’s thesis. A funded PhD position will subsequently be available, offering an opportunity to continue this research. Localisation du poste Site Grenoble Localisation du poste France, Auvergne-Rhône-Alpes, Isère (38) Ville Grenoble Critères candidat Langues
• Anglais (Intermédiaire)
• Français (Courant) Diplôme préparé Bac+5
- Diplôme École d'ingénieurs Formation recommandée Master 2 / Ecole d'ingénieurs Possibilité de poursuite en thèse Oui Demandeur Disponibilité du poste 01/02/2027

Internship Hybrid DRAM: Next-Gen ferroelectric memory for energy-constrained systems-Grenoble-H/F

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Internship Hybrid DRAM: Next-Gen ferroelectric memory for energy-constrained systems-Grenoble-H/F

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Villes principales