Verification Engineer

Overview/Job Summery We are looking for a highly experienced Senior Staff ASIC Verification Engineer to lead the verification of complex digital designs. The ideal candidate will have deep expertise in advanced verification methodologies, strong leadership skills, and a proven track record of successfully verifying sophisticated SoCs/ASICs from concept to silicon.

Job Description
Technical Leadership
• Lead end-to-end verification of complex digital IP blocks and subsystems
• Define and implement comprehensive verification strategies and test plans
• Develop advanced UVM testbench architectures and reusable verification components
• Drive coverage closure and sign-off quality metrics
• Perform block-level and system-level verification Methodology & Infrastructure
• Develop and enhance verification methodologies and flows
• Create and maintain advanced verification infrastructure using Python/Perl/TCL scripting
• Build behavioral models and reference models for complex protocols
• Implement coverage-driven and assertion-based verification strategies
• Optimize simulation performance and regression efficiency Collaboration & Mentorship
• Work closely with design, architecture, system, and physical implementation teams
• Provide technical mentorship to junior and mid-level verification engineers
• Conduct design and testplan reviews
• Lead debug efforts for complex functional and timing issues
• Drive best practices and process improvements across the verification team Project Leadership
• Own verification schedules and deliverables for assigned blocks
• Identify project risks and develop mitigation strategies
• Present verification status and quality metrics to management
• Participate in post-silicon validation and debug Qualifications Experience
• 10+ years of hands-on ASIC/FPGA verification experience
• 5+ years of experience with UVM methodology
• Proven track record of multiple successful tape-outs
• Experience leading verification projects from specification to silicon Technical Skills Verification Methodologies:
• Expert-level proficiency in SystemVerilog and UVM
• Deep understanding of constrained random verification
• Functional coverage and code coverage analysis
• Assertion-based verification (SVA)
• Experience with formal verification tools (bonus) Tools & Simulators:
• Required: Cadence simulation tools (Xcelium/IES/SimVision)
• Highly Preferred: Synopsys VCS and DVE
• Experience with debug tools and waveform viewers
• Familiarity with coverage tools (IMC, URG, or equivalent) Scripting & Programming:
• Strong proficiency in Python and/or Perl
• Experience with TCL scripting
• Shell scripting (bash/csh)
• Makefile development
• Familiarity with version control (Git, SOS) Modeling:
• C/C++ or SystemC for reference model development
• Bus functional models (BFM) development
• Protocol monitors and checkers
• Performance modeling experience (plus) Technical Knowledge:
• Strong understanding of RTL design principles
• Experience with industry-standard protocols (e.g., AMBA AHB/APB,I2C/SPI/I3C,.. etc.)
• Knowledge of low-power verification techniques (UPF)
• Knowledge of Gate Level Simulation verification Education
• BS in Electrical Engineering, Computer Engineering, or Computer Science required
• MS or PhD preferred Preferred Qualifications
• Experience with Synopsys VCS simulator and associated tools
• Formal verification experience (JasperGold, VC Formal)
• Post-silicon validation and bring-up experience
• Experience with RISC-V, or other processor architectures
• Mixed-signal verification experience
• Knowledge of machine learning/AI accelerator verification Key Competencies Technical Excellence:
• Deep analytical and problem-solving skills
• Ability to debug complex, multi-million gate designs
• Strong understanding of verification quality metrics Leadership & Communication:
• Excellent written and verbal communication skills
• Ability to mentor and develop engineering talent
• Cross-functional collaboration and influence
• Technical presentation skills Personal Attributes:
• Self-motivated with strong ownership mentality
• Detail-oriented with quality focus
• Adaptable to changing priorities
• Passion for innovation and continuous learning Application Process Interested candidates should submit: 1. Current resume/CV 2. Cover letter highlighting relevant experience 3. Links to any publications or GitHub projects (optional) InvenSense, a TDK group company, is a world-leading provider of MEMS and magnetic sensor solutions found in mobile, wearable, smart home, AR/VR, and other consumer and IoT applications. We are innovators with a 20+ year history of patented sensor technologies. As experts in our field, we lead industry breakthroughs in consumer, industrial and automotive technology and reliably deliver high-quality solutions to our partners across global markets. Learn more

about us
at invensense.tdk.com Contact: mohamed.ayoujil@tdk.com