Senior PCIe/CXL RTL Design Architect
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Rambus is seeking a Senior Design engineer in Aix-en-Provence to contribute to architecture and micro-architecture of PCIe/CXL/IP. The role involves SystemVerilog implementation and collaboration with verification teams, including prototyping IPs on FPGAs.
You will join a hybrid setup with onsite and remote work, joining a multicultural team. A Master’s or PhD in EE/CE and 5+ years RTL design experience are expected, with strong English communication skills.