Verification Engineer

Overview/Job Summery

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We are looking for a highly experienced Senior Staff ASIC Verification Engineer to lead the verification of complex digital designs. The ideal candidate will have deep expertise in advanced verification methodologies, strong leadership skills, and a proven track record of successfully verifying sophisticated SoCs/ASICs from concept to silicon.

Job Description
Technical Leadership

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• Lead end-to-end verification of complex digital IP blocks and subsystems
  
• Define and implement comprehensive verification strategies and test plans
  
• Develop advanced UVM testbench architectures and reusable verification components
  
• Drive coverage closure and sign-off quality metrics
  
• Perform block-level and system-level verification
  

Methodology & Infrastructure

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• Develop and enhance verification methodologies and flows
  
• Create and maintain advanced verification infrastructure using Python/Perl/TCL scripting
  
• Build behavioral models and reference models for complex protocols
  
• Implement coverage-driven and assertion-based verification strategies
  
• Optimize simulation performance and regression efficiency
  

Collaboration & Mentorship

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• Work closely with design, architecture, system, and physical implementation teams
  
• Provide technical mentorship to junior and mid-level verification engineers
  
• Conduct design and testplan reviews
  
• Lead debug efforts for complex functional and timing issues
  
• Drive best practices and process improvements across the verification team
  

Project Leadership

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• Own verification schedules and deliverables for assigned blocks
  
• Identify project risks and develop mitigation strategies
  
• Present verification status and quality metrics to management
  
• Participate in post-silicon validation and debug
  

Qualifications
Experience

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• 10+ years of hands-on ASIC/FPGA verification experience
  
• 5+ years of experience with UVM methodology
  
• Proven track record of multiple successful tape‑outs
  
• Experience leading verification projects from specification to silicon
  

Technical Skills
Verification Methodologies:

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• Expert‑level proficiency in SystemVerilog and UVM
  
• Deep understanding of constrained random verification
  
• Functional coverage and code coverage analysis
  
• Assertion‑based verification (SVA)
  
• Experience with formal verification tools (bonus)
  

Tools & Simulators:

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• Required: Cadence simulation tools (Xcelium/IES/SimVision)
  
• Highly Preferred: Synopsys VCS and DVE
  
• Experience with debug tools and waveform viewers
  
• Familiarity with coverage tools (IMC, URG, or equivalent)
  

Scripting & Programming:

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• Strong proficiency in Python and/or Perl
  
• Experience with TCL scripting
  
• Shell scripting (bash/csh)
  
• Makefile development
  
• Familiarity with version control (Git, SOS)
  

Modeling:

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• C/C++ or SystemC for reference model development
  
• Bus functional models (BFM) development
  
• Protocol monitors and checkers
  
• Performance modeling experience (plus)
  

Technical Knowledge:

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• Strong understanding of RTL design principles
  
• Experience with industry‑standard protocols (e.g., AMBA AHB/APB,I2C/SPI/I3C,.. etc.)
  
• Knowledge of low‑power verification techniques (UPF)
  
• Knowledge of Gate Level Simulation verification
  

Education

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• BS in Electrical Engineering, Computer Engineering, or Computer Science required
  
• MS or PhD preferred
  

Preferred Qualifications

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• Experience with Synopsys VCS simulator and associated tools
  
• Formal verification experience (JasperGold, VC Formal)
  
• Post-silicon validation and bring‑up experience
  
• Experience with RISC‑V, or other processor architectures
  
• Mixed‑signal verification experience
  
• Knowledge of machine learning/AI accelerator verification
  

Key Competencies
Technical Excellence:

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• Deep analytical and problem‑solving skills
  
• Ability to debug complex, multi‑million gate designs
  
• Strong understanding of verification